The present disclosure relates to a semiconductor device and a method of manufacturing the same.
In recent years, miniaturization, high functionality and speeding up of electronic devices such as computers, cellular phones, and PDAs (Personal Digital Assistances) have progressed. Therewith, miniaturization, speeding up, and high density of semiconductor devices such as ICs (integrated circuits) and LSIs (large-scale integrated circuits) for such electronic devices are necessary.
Miniaturization, speeding up and high density of semiconductor devices have a tendency to cause an increase in power consumption, and to increase the amount of heat generation per unit volume.
In the past, as mounting structures of a semiconductor chip, structures have been used in which a semiconductor chip is mounted on a substrate in a flip-chip manner using a solder bump, in the state where the surface on which an electrode of the semiconductor chip is formed is faced down.
In the semiconductor device in which flip-chip mounting is performed, there is a problem that stress is generated in the junction portion through the solder bump by the heat generation due to a difference in the coefficients of thermal expansion between a semiconductor chip and a substrate, and the connection reliability is deteriorated.
Similarly, when the amount of warpage of the semiconductor device in which the semiconductor chip is mounted in a flip-chip manner is large, there is a problem that the secondary mounting reliability at the time of mounting the semiconductor device on a mounting substrate is deteriorated.
In order to solve such problems, a semiconductor device is proposed in which a gap between a semiconductor chip and a substrate is filled with an underfill and is hardened, and a portion of the substrate is covered with a resin layer (see, for example, Japanese Unexamined Patent Application Publication No. 2007-335740).
That is, for example, a gap between a substrate 101 and a semiconductor chip 102 located thereon is filled with an underfill 105, as shown in FIG. 7A illustrating a perspective view of the semiconductor device and FIG. 7B illustrating a cross-sectional view taken along the line VIIB-VIIB of FIG. 7A.
The substrate 101 and the semiconductor chip 102 are electrically connected to each other by electrode pads 103 on the surface (upper surface in the drawing) of the substrate 101 and solder bumps 104 on the lower surface of the semiconductor chip 102. The underfill 105 is filled in the portions other than those in which the electrode pads 103 and the solder bumps 104 are connected to each other.
A semiconductor device 100 is formed by covering the substrate 101 around the semiconductor chip 102 with a resin layer 110.
In addition, solder balls 106 are formed on the backside (lower surface in the drawing) of the substrate 101.
With such a configuration, since stress applied to the solder bump is relaxed by the underfill and the resin layer on the substrate, the connection reliability is improved. In addition, it is possible to suppress deformation caused by external forces to the substrate.